View GRM155R71C103KA01D_8320052.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

6bit 0.5 db digital step attenuator 100 mhz to 4000 mhz glitchfree tm digital step attenuator 1 rev2 april 2013 idt f195 1 datasheet g eneral d escription this document describes the specification for the idtf1951 digital step attenuator. the f1951 is par t of a family of glitchfree tm dsas optimized for the demanding requirements of communications infrastructure. the se devices are offered in a compact 4x4 qfn package wi th 50 impedances for ease of integration into the radio system. c ompetitive a dvantage digital step attenuators are used in receivers and transmitters to provide gain control. the idtf1951 is a 6bit step attenuator optimized for these demanding applications. the silicon design has very low inse rtion loss and low distortion (+65 dbm ip3 i .) the device has pinpoint accuracy and settles to final attenuation value within 400 nsec. most importantly, the f1951 inclu des idts g g l l i i t t c c h h - - f f r r e e e e t t m m technology which results in less than 0.6 db of overshoot ringing during msb transit ions. this is in stark contrast to competing dsas that glitch as much as 10 db during msb transitions (see p.10) l l o o w w e e s s t t i i n n s s e e r r t t i i o o n n l l o o s s s s f f o o r r b b e e s s t t s s n n r r g g l l i i t t c c h h f f r r e e e e t t m m w w h h e e n n t t r r a a n n s s i i t t i i o o n n i i n n g g C C w w o o n n t t d d a a m m a a g g e e p p a a o o r r a a d d c c e e x x t t r r e e m m e e l l y y a a c c c c u u r r a a t t e e w w i i t t h h l l o o w w d d i i s s t t o o r r t t i i o o n n a pplications ? base station 2g, 3g, 4g, tdd radiocards ? repeaters and e911 systems ? digital predistortion ? point to point infrastructure ? public safety infrastructure ? wimax receivers and transmitters ? military systems, jtrs radios ? rfid handheld and portable readers ? cable infrastructure p art # m atrix part# freq range resolution / range control il pinout f f 1 1 9 9 5 5 1 1 1 1 0 0 0 0 4 4 0 0 0 0 0 0 0 0 . . 5 5 0 0 / / 3 3 1 1 . . 5 5 s s e e r r i i a a l l o o n n l l y y 1 1 . . 2 2 h h i i t t t t f1950 150 4000 0.25 / 31.5 serial only 1.3 pe f1952 100 C 4000 0.50 / 15.5 serial only 0.9 hitt f eatures ? glitchfree tm , < 0.6 db transient overshoot ? spurious free design ? 3v to 5v supply ? attenuation error < 0.2 db @ 2 ghz ? low insertion loss < 1.2 db @ 2 ghz ? excellent linearity +65 dbm ip3 i ? fast settling time, < 450 nsec ? class 2 jedec esd (> 2kv hbm) ? serial interface 31.5 db range ? stable integral nonlinearity over temperature ? 4x4 mm thin qfn 24 pin package d evice b lock d iagram o rdering i nformation rf 1 bias v dd dec spi rf 2 rst clk cs sdi sdo idt f1951nbgi8 0.8 mm height package green industrial temp range tape & reel omit idt prefix rf product line glitch-free tm glitch-free tm
6bit 0.5 db digital step attenuator 100 mhz to 4000 mhz glitchfree tm digital step attenuator 2 rev2 april 2013 idt f195 1 datasheet a bsolute m aximum r atings v dd to gnd 0.3v to +5.25v d[5:0], data, clk,csb,sdo, rstb 0.3v to 3.6v rf input power (rf1, rf2) calibration and testing + 29 dbm rf input power (rf1, rf2) continuous rf operation + 23 dbm ja (junction C ambient) +50c/w jc (junction C case) the case is defined as the exposed paddle +3c/w operating temperature range (case temperature) t c = 40c to +100c maximum junction temperature 140c storage temperature range 65c to +150c lead temperature (soldering, 10s) . +260c
6bit 0.5 db digital step attenuator 100 mhz to 4000 mhz glitchfree tm digital step attenuator 3 rev2 april 2013 idt f195 1 datasheet idtf1951 s pecification (31.5 db range) specifications apply at v dd = +3.3v , f rf = 2000mhz , t c = +25c unless otherwise noted, evkit losses are de embedded (see p. 17) parameter comment sym. min typ ical max units logic input high clk, csb, data, d[5:0], rstb v ih 2.3 3.6 v logic input low clk, csb, data, d[5:0], rstb v il 0.7 v logic current v mode i ih, i il -5 +5 a supply voltage(s) main supply v dd 3.0 to 5.25 v supply current total i dd 1.1 2 1 ma temperature range operating range (case) t c 40 to +100 degc frequency range operating range f rf 100 to 4000 mhz rf1, rf2 return loss db(s11), db(s22) s 11 , s 22 22 db minimum attenuation d[5:0] = [111111] a m in or il 1.2 1.9 db maximum attenuation ? d[5:0] = [000000] ? v dd = 3.3v a max 32.2 32.5 db minimum gain step least significant bit lsb 0.50 db phase delta phase change a min vs. a max ? 33 deg differential nonlinearity error: adjacent steps dnl 0.08 db integral nonlinearity error: absolute to 14 db attn inl 1 0.03 0.34 db integral nonlinearity max error vs. line (a min ref) to 31.5 db attn [v dd = 3.3v] inl 2 0.21 0.38 db input ip3 d[5:0] = [111111] = a min d[5:0] = [100000] = a 15.5 d[5:0] = [000000] = a max p in = +10 dbm per tone 50 mhz tone separation v dd = 3.3v ip3i 1 ip3i 2 ip3i 3 +61 2 +59 +57 +64 +61 +61 dbm 0.1 db compression please note abs max d[5:0] = [111010] = a 2.5 baseline p in = 20 dbm p 0.1 29 dbm settling time start le rising edge > v ih end +/0.10 db pout settling 15.5 C 16.0 transition t lsb 400 nsec serial clock speed spi 4 wire bus f cl k 20 50 mhz reset to serial setup spi 4 wire bus a 20 nsec serial data hold time spi 4 wire bus b 5 nsec csb setup delay spi 4 wire bus c 40 100 nsec serial data out delay spi 4 wire bus d 8 8 8 cycles s pecification n otes : 1 C items in min/max columns in bold italics are guaranteed by test 2 C all other items in min/max columns are guarante ed by design characterization
6bit 0.5 db digital step attenuator 100 mhz to 4000 mhz glitchfree tm digital step attenuator 4 rev2 april 2013 idt f195 1 datasheet s erial c ontrol m ode data is clocked in lsb first via serial mode. note the timing diagram below. an rstb pulse resets the shift register to [0000000 0]. if the rstb pulse is followed immediately by a csb pulse the device will be set to maximum attenuation . note C the idtf1951 includes a clk inhibit feature designe d to minimize sensitivity to clk bus noise when the device is not being programmed. when csb is high (> v ih ), the clk input is disabled and serial data (sdi) will not be clocked into the shift register. it is recommended that csb be pulled high (>v ih ) when the device is not being programmed s erial r egister t iming d iagram [s ingle d evice ]: (note the timing spec intervals in blue ) s erial r egister t iming d iagram [t wo or more devices ]: the contents of the shift register is delayed by 8 clock cycles while csb is low. this feature allows one to program multiple dsas (in a mimo transceiver for instance) with a single common csb line by daisychaining the sdo of the 2 nd dsa to the sdi of the 1 st dsa and so forth:
6bit 0.5 db digital step attenuator 100 mhz to 4000 mhz glitchfree tm digital step attenuator 5 rev2 april 2013 idt f195 1 datasheet s erial r egister d efault c ondition [f1951]: when the device is first powered up, it will defaul t to the maximum attenuation setting as described below: note that for the f1951 (high or 1) = attenuation s tepped out . (0 or low) = attenuation stepped in . s erial r egister t iming t able [f1951]: interval symbol description min spec max spec units a reset to serial setup time 20 nsec b serial data hold time 5 nsec c csb setup delay 40 100 nsec d serial data out delay 8 8 cycles default register settings 0 0 0 0 0 0 0 0 r0 r1 d3 d0 d2 d1 lsb d5 msb d4 rsv rsv
6bit 0.5 db digital step attenuator 100 mhz to 4000 mhz glitchfree tm digital step attenuator 6 rev2 april 2013 idt f195 1 datasheet t ypical o perating p arametric c urves (evkit loss de-embedded, 3.3v unless otherwise not ed) insertion loss vs. frequency [a min ] s 11 vs. frequency [t case = +25c, 0.5 db steps] s 11 vs. attenuation state attenuation vs. freq [t case = +25c, 0.5 db steps] s 22 vs. frequency [t case = +25c, 0.5 db steps] s 22 vs. attenuation state 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 200 600 1000 1400 1800 2200 2600 3000 3400 3800 40 degc 3.3 v 25 degc 3.3 v 100 degc 3.3 v rf frequency (mhz) insertion loss (db) 40 35 30 25 20 15 10 5 0 200 600 1000 1400 1800 2200 2600 3000 3400 3800 rf frequency (mhz) rf frequency (mhz) rf frequency (mhz) rf frequency (mhz) rf1 return loss (db) 40 35 30 25 20 15 10 5 0 0 4 8 12 16 20 24 28 40 degc 900 mhz 40 degc 2000 mhz 25 degc 900 mhz 25 degc 2000 mhz 100 degc 900 mhz 100 degc 2000 mhz attenuation setting (db) rf1 return loss (db) 35 30 25 20 15 10 5 0 200 600 1000 1400 1800 2200 2600 3000 3400 3800 rf frequency (mhz) rf frequency (mhz) rf frequency (mhz) rf frequency (mhz) dsa loss (db) 40 35 30 25 20 15 10 5 0 200 600 1000 1400 1800 2200 2600 3000 3400 3800 rf frequency (mhz) rf frequency (mhz) rf frequency (mhz) rf frequency (mhz) rf2 return loss (db) 40 35 30 25 20 15 10 5 0 0 4 8 12 16 20 24 28 40 degc 900 mhz 40 degc 2000 mhz 25 degc 900 mhz 25 degc 2000 mhz 100 degc 900 mhz 100 degc 2000 mhz attenuation setting (db) rf2 return loss (db) attenuation setting (db) rf1 return loss (db)
6bit 0.5 db digital step attenuator 100 mhz to 4000 mhz glitchfree tm digital step attenuator 7 rev2 april 2013 idt f195 1 datasheet toc s continued (-2-) phase vs. frequency supply current i dd input ip3 [f rf = 1900 mhz] phase vs. attenuation setting input ip3 [f rf = 900 mhz] compression [f rf = 2000 mhz, attn = 2.5 db] 110 100 90 80 70 60 50 40 30 20 10 0 10 200 600 1000 1400 1800 2200 2600 3000 3400 3800 40 degc 31.5 db 40 degc 0.0 db 25 degc 31.5 db 25 degc 0.0 db 100 degc 31.5 db 100 degc 0.0 db rf frequency (mhz) s21 phase (degrees) 0.00 0.25 0.50 0.75 1.00 1.25 1.50 0 4 8 12 16 20 24 28 40 degc 3.3 v 25 degc 3.3 v 100 degc 3.3 v total i dd (ma) attenuation setting (db) 10 20 30 40 50 60 70 80 90 0 4 8 12 16 20 24 28 40 degc 5.0 v 40 degc 3.3 v 25 degc 5.0 v 25 degc 3.3 v 100 degc 5.0 v 100 degc 3.3 v attenuation setting (db) input ip3 (dbm) 100 90 80 70 60 50 40 30 20 10 0 0 4 8 12 16 20 24 28 100 mhz 400 mhz 900 mhz 1400 mhz 1900 mhz 2400 mhz 2900 mhz 3400 mhz 3900 mhz attenuation setting (db) s21 phase (degrees) 10 20 30 40 50 60 70 80 90 0 4 8 12 16 20 24 28 40 degc 5.0 v 40 degc 3.3 v 25 degc 5.0 v 25 degc 3.3 v 100 degc 5.0 v 100 degc 3.3 v attenuation setting (db) input ip3 (dbm) 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 20 21 22 23 24 25 26 27 28 29 40 degc 5.0 v 40 degc 3.3 v 25 degc 5.0 v 25 degc 3.3 v 100 degc 5.0 v 100 degc 3.3 v loss compression (db) attenuation setting (db)
6bit 0.5 db digital step attenuator 100 mhz to 4000 mhz glitchfree tm digital step attenuator 8 rev2 april 2013 idt f195 1 datasheet toc s continued (-3-) dnl [150 mhz] dnl [900 mhz] dnl [2800 mhz] dnl [400 mhz] dnl [1900 mhz] worst setting dnl 0.75 0.50 0.25 0.00 0.25 0.50 0.75 0 4 8 12 16 20 24 28 40 degc 25 degc 100 degc attenuation setting (db) attenuation setting (db) step error (db) 0.75 0.50 0.25 0.00 0.25 0.50 0.75 0 4 8 12 16 20 24 28 40 degc 25 degc 100 degc attenuation setting (db) attenuation setting (db) step error (db) 0.75 0.50 0.25 0.00 0.25 0.50 0.75 0 4 8 12 16 20 24 28 40 degc 25 degc 100 degc attenuation setting (db) attenuation setting (db) step error (db) 0.75 0.50 0.25 0.00 0.25 0.50 0.75 0 4 8 12 16 20 24 28 40 degc 25 degc 100 degc attenuation setting (db) attenuation setting (db) step error (db) 0.75 0.50 0.25 0.00 0.25 0.50 0.75 0 4 8 12 16 20 24 28 40 degc 25 degc 100 degc attenuation setting (db) attenuation setting (db) step error (db) 1.00 0.75 0.50 0.25 0.00 0.25 0.50 0.75 1.00 100 500 900 1300 1700 2100 2500 2900 3300 3700 40 degc min of dnl (db) 40 degc max of dnl (db) 25 degc min of dnl (db) 25 degc max of dnl (db) 100 degc min of dnl (db) 100 degc max of dnl (db) rf frequency (mhz) worst setting step error (db)
6bit 0.5 db digital step attenuator 100 mhz to 4000 mhz glitchfree tm digital step attenuator 9 rev2 april 2013 idt f195 1 datasheet toc s continued (-4-) inl [150 mhz] inl [900 mhz] inl [2900 mhz] inl [400 mhz] inl [1900 mhz] worst setting inl 1.50 1.25 1.00 0.75 0.50 0.25 0.00 0.25 0 4 8 12 16 20 24 28 40 degc 25 degc 100 degc attenuation setting (db) attenuation setting (db) absolute error (db) attenuation setting (db) 1.50 1.25 1.00 0.75 0.50 0.25 0.00 0.25 0 4 8 12 16 20 24 28 40 degc 25 degc 100 degc attenuation setting (db) attenuation setting (db) absolute error (db) attenuation setting (db) 1.50 1.25 1.00 0.75 0.50 0.25 0.00 0.25 0 4 8 12 16 20 24 28 40 degc 25 degc 100 degc attenuation setting (db) attenuation setting (db) absolute error (db) attenuation setting (db) 1.50 1.25 1.00 0.75 0.50 0.25 0.00 0.25 0 4 8 12 16 20 24 28 40 degc 25 degc 100 degc attenuation setting (db) attenuation setting (db) absolute error (db) attenuation setting (db) 1.50 1.25 1.00 0.75 0.50 0.25 0.00 0.25 0 4 8 12 16 20 24 28 40 degc 25 degc 100 degc attenuation setting (db) attenuation setting (db) absolute error (db) attenuation setting (db) 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 0.5 1.0 100 500 900 1300 1700 2100 2500 2900 3300 3700 40 degc 25 degc 100 degc rf frequency (mhz) worst setting absolute error (db) rf frequency (mhz)
6bit 0.5 db digital step attenuator 100 mhz to 4000 mhz glitchfree tm digital step attenuator 10 rev2 april 2013 idt f195 1 datasheet toc s continued (-5-) [f rf = 900 mhz] transient [ 15.5 to 16.0 (msb+) 3.3v f1951 ] the graphs above show the transient overshoot and settling time performance for both the msb+ and msb cases for the f1951. the device settles very quickly (~400) nsec with benign (~0.5) db overshoot . transient [ 15.75 to 16.00 (msb+) standard dsa ] transient [ 16.0 to 15.5 (msb-) 5.0v f1951 ] the graphs below show the transient overshoot and settling time performance for a popular competing dsa. n n o o t t e e t t h h e e o o v v e e r r s s h h o o o o t t / / u u n n d d e e r r s s h h o o o o t t e e x x c c u u r r s s i i o o n n o o f f a a l l m m o o s s t t 1 1 0 0 d d b b and the very long settling time. for the msb case, the settling time is off the scale, ~ 3 usec. transient [ 16.00 to 15.75 (msb-) standard dsa ] 1.0 0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 20.0 19.0 18.0 17.0 16.0 15.0 14.0 13.0 12.0 11.0 10.0 100 0 100 200 300 400 500 600 700 le trigger (volts) envelope power (dbm) time (nsec) glitch ~ 0.5 db pwr (dbm) trigger settling time = 400 nsec (+/- 0.1 db) 1.0 0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 15.20 14.20 13.20 12.20 11.20 10.20 9.20 8.20 7.20 6.20 5.20 100 0 100 200 300 400 500 600 700 le trigger (volts) envelope power (dbm) time (nsec) pwr (dbm) trigger settling time = 600nsec (+/- 0.1 db) 1.0 0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 20.0 19.0 18.0 17.0 16.0 15.0 14.0 13.0 12.0 11.0 10.0 100 0 100 200 300 400 500 600 700 le trigger (volts) envelope power (dbm) time (nsec) glitch ~ 0.5 db pwr (dbm) trigger settling time = 390 nsec (+/- 0.1 db) 1.0 0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 13.57 12.57 11.57 10.57 9.57 8.57 7.57 6.57 5.57 4.57 3.57 100 0 100 200 300 400 500 600 700 le trigger (volts) envelope power (dbm) time (nsec) pwr (dbm) trigger settling time >> 1 usec
6bit 0.5 db digital step attenuator 100 mhz to 4000 mhz glitchfree tm digital step attenuator 11 rev2 april 2013 idt f195 1 datasheet p in d iagram (f1951) nc gnd [internal nc] nc nc *rf2 sdo nc v dd gnd [internal nc] *rf1 nc exposed pad 2 1 3 5 4 6 package drawing 4 mm x 4 mm package dimension 2.80 mm x 2.80 mm exposed pad 0.5 mm pitch 24 pins 0.75 mm height 0.25 mm pad width 0.40 mm pad length 14 13 15 17 16 18 8 7 9 11 10 12 20 19 21 23 22 24 nc c o 0 .3 5 m m top view (looking through the top of the package) * device is rf bi-directional
6bit 0.5 db digital step attenuator 100 mhz to 4000 mhz glitchfree tm digital step attenuator 12 rev2 april 2013 idt f195 1 datasheet p ackage d rawing (4 x 4 24 pin )
6bit 0.5 db digital step attenuator 100 mhz to 4000 mhz glitchfree tm digital step attenuator 13 rev2 april 2013 idt f195 1 datasheet p in d escriptions pin # pin name pin function 1 nc internally unconnected. recommended connection is gnd. 2 rf1 device rf input or output (bidirectional). must a c couple to this pin. 3 gnd connect directly to paddle ground or as close as po ssible to pin with thru via. 4 nc internally unconnected. recommended connection is gnd. 5 sdo serial data outdelayed 8 clock cycles from serial data in. 6 nc internally unconnected. recommended connection is gnd. 7 rstb reset bar. falling edge resets the device to max a ttenuation [d5:d0] = [000000]. 8 clk serial clock. 9 csb chip select bar. serial data latched into active r egister on rising edge. 10 nc internally unconnected. recommended connection is gnd. 11 sdi serial data input. 12 nc internally unconnected. recommended connection is gnd. 13 nc internally unconnected. 14 vdd main supply. use 3.3v or 5v. current is < 1 ma. 15 nc internally unconnected. recommended connection is gnd. 16 gnd connect directly to paddle ground or as close as po ssible to pin with thru via. 17 rf2 device rf output or input (bidirectional). must a c couple to this pin. 18 nc internally unconnected. recommended connection is gnd. 19 gnd connect directly to paddle ground or as close as po ssible to pin with thru via. 20 gnd connect directly to paddle ground or as close as po ssible to pin with thru via. 21 gnd connect directly to paddle ground or as close as po ssible to pin with thru via. 22 gnd connect directly to paddle ground or as close as po ssible to pin with thru via. 23 gnd connect directly to paddle ground or as close as po ssible to pin with thru via. 24 gnd connect directly to paddle ground or as close as po ssible to pin with thru via. ep exposed paddle connect to ground with multiple vias for good therm al relief.
6bit 0.5 db digital step attenuator 100 mhz to 4000 mhz glitchfree tm digital step attenuator 14 rev2 april 2013 idt f195 1 datasheet ev kit s chematic the diagram below describes the recommended applica tions / evkit circuit: j1 gnd nc gnd rf1 sdo nc rf2 nc nc v dd nc c13 c14 u1 14 13 15 17 16 18 2 1 3 5 4 6 20 19 21 23 22 24 8 7 9 11 10 12 j3 rf1 j2 v dd nc j5 vdd c12 c11 j4 rf2 j6 16 + o 1 + o 2 + o 3 + o 4 + o 5 + o 6 + o 7 + o 8 + 9 j2 j7 c1 c2 r1 c3 r3 r4 r5 r6 r7 r8 4 pin header parallel control switch (not placed) vlh 8 pin header c4 c5 c6 c7 c8 c9 r2 r1 c10 c15 c16 c17 r9 r10 r11 r12 tp1 idtf1951
6bit 0.5 db digital step attenuator 100 mhz to 4000 mhz glitchfree tm digital step attenuator 15 rev2 april 2013 idt f195 1 datasheet evk it o peration (email: rfsupport@idt.com to request an evkit, serial control hw/sw , or trl cal board) the picture and graphic below describe how to opera te the evkit rf2 dc power unused rf1 sdo sdi csb clk rstb
6bit 0.5 db digital step attenuator 100 mhz to 4000 mhz glitchfree tm digital step attenuator 16 rev2 april 2013 idt f195 1 datasheet evk it bom t op m arkings f1951 bom rev 02 pcb rev 01 item # value size description mfr. part # mfr. ref des qty 1 1000pf 0402 cap cer 1000pf 50v c0g 0402 grm1555c1h102ja01d murata c13,14 2 2 10nf 0402 cap cer 10000pf 16v 10% x7r 0402 GRM155R71C103KA01D murata c12 1 3 0.1uf 0402 cap cer 0.1uf 16v 10% x7r 0402 grm155r71c104ka88d murata c11 1 4 header 2 pin th 2 conn header vert sgl 2pos gold 9611026404ar 3m j5 1 5 header 4 pin th 4 conn header vert sgl 4pos gold 9611046404ar 3m j8 1 6 header 8 pin th 8 conn header vert sgl 8pos gold 9611086404ar 3m j6 1 7 sma_end_launch .062 sma_end_launch (small) 1420711821 emerson johnson j2,3,4 3 8 0 0402 res 0.0 ohm 1/10w 0402 smd erj2ge0r00x panasonic r7,8,10 3 9 3k 0402 res 3.00k ohm 1/10w 1% 0402 smd erj2rkf3001x panasonic r3,5,6 3 10 digital step attenuator f1951 f1951 idt u2 1 11 pcb pcb rev 01 f195xs evkit rev 01 1 total 18 10/26/2012 idtf19 51nbgi z207aga lot code part number
6bit 0.5 db digital step attenuator 100 mhz to 4000 mhz glitchfree tm digital step attenuator 17 rev2 april 2013 idt f195 1 datasheet evk it t hrough -r eflect -l ine (trl) c alibration the throughreflectline (trl) method [1] is used to deembed the evaluation board losses from the s parameter measurements of the f1951. this method requires the use of three standa rds: a through, a reflection, and a line. the trl m ethod has the advantage over other calibration methods in that it requires only one of these three standards to be well defined. the trl through which is used for the f1951 trl cal ibration was constructed identically to the evaluat ion board, minus the dut and its corresponding length. therefore, the through corres ponds to a precise zero length connection between t he input and output reference planes of the dut. this through satisfies the requi rement of the trl method that one of the three stan dards be precisely specified. the trl reflection standard used is constructed ide ntically to the input and output lines of the evalu ation board, with a short placed at the reference plane of the dut. in accordance with the trl methods requirements, the actual magnitude and phase were not accurately specified, but the phase was known to within 90 deg rees and the trl reflection standard has a magnitud e close to one. the trl line standard is identical to the trl throu gh, but with an additional length of 0.8 inches (2 cm). this satisfies the trl methods requirement that the trl be a different length than the trl through, that it have the same impedance a nd propagation constant as the through, and that the phase difference between the through and the line be between 20 degrees and 160 degrees. the difference in length yields a phase difference of approximately 20 degre es at 500 mhz, and a phase difference of 160 degree s at 4 ghz. for characterization of performance from 150 to 500 mhz a separate trl board with different line len gth is used. standards used for f195x trl calibration f1951 evaluation circuit engen, g.f.; hoer, c.a.; thrureflectline: an i mproved technique for calibrating the dual sixport automatic network analyzer, ieee transactions on microwave theory and techniques , volume: 27 issue:12, pp. 987 C 993, dec 1979.

▲Up To Search▲

Price & Availability of GRM155R71C103KA01D

	To Download GRM155R71C103KA01D Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .